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table of contents 1 overview ................................ ................................ ................................ ................................ ........... 5 1.1 overview ................................ ................................ ................................ ................................ .... 5 1.2 applications ................................ ................................ ................................ ................................ 5 1.3 features ................................ ................................ ................................ ................................ ..... 5 2 pin information ................................ ................................ ................................ ................................ .. 7 2.1 pin configuration ................................ ................................ ................................ ........................ 7 2.2 pin description ................................ ................................ ................................ ............................ 8 3 functional block diagram ................................ ................................ ................................ ................ 11 3.1 system block diagram ................................ ................................ ................................ .............. 1 1 3.2 functional block diagram ................................ ................................ ................................ ......... 15 4 solution circuit for application ................................ ................................ ................................ ......... 16 5 functional description ................................ ................................ ................................ ....................... 17 5.1 clock systems and system operation modes ................................ ................................ ........... 17 5.2 de-interlace ................................ ................................ ................................ .............................. 19 5.3 timing generator ................................ ................................ ................................ ...................... 20 5.4 scaler ................................ ................................ ................................ ................................ ....... 21 5.5 boost-up ................................ ................................ ................................ ................................ ... 21 5.6 osd (on-screen display) ................................ ................................ ................................ ......... 22 5.7 gamma ................................ ................................ ................................ ................................ .... 31 5.8 contrast control ................................ ................................ ................................ ........................ 32 5.9 dither ................................ ................................ ................................ ................................ ........ 32 5.10 test pattern generator (tpg) ................................ ................................ ................................ . 33 5.11 i2c host interface protocol ................................ ................................ ................................ ..... 35 6 register map ................................ ................................ ................................ ................................ ... 38 6.1 global control registers ................................ ................................ ................................ ........... 38 6.2 timing generator control registers ................................ ................................ .......................... 42 6.3 de-interlace control registers ................................ ................................ ................................ .. 48 6.4 image scaling control registers ................................ ................................ ............................... 53 6.5 advanced color contrast enhancement (ace) control registers ................................ ............. 55 6.6 global image gain & offset control register ................................ ................................ ............ 60 6.7 osd control registers ................................ ................................ ................................ .............. 64 6.8 gamma correction control register ................................ ................................ ......................... 74 6.9 osd ram control registers ................................ ................................ ................................ ..... 77
table of contents (continued) 7 electrical specification ................................ ................................ ................................ ..................... 78 7.1 absolute maximum ratings ................................ ................................ ................................ ...... 78 7.2 recommended operation conditions ................................ ................................ ....................... 78 7.3 dc electrical characteristics ................................ ................................ ................................ ..... 79 7.4 ac electrical characteristics ................................ ................................ ................................ ..... 80 8 package dimension ................................ ................................ ................................ ......................... 82 8.1 100-tqfp-1414 ................................ ................................ ................................ ........................ 82 9 fonts ................................ ................................ ................................ ................................ ........... 83
figure of contents figure 1 S5D2400X pin configuration ................................ ................................ .................... 7 figure 2 S5D2400X system block diagram (itu-r bt.656 input to single rgb output) ..... 11 figure 3 S5D2400X system block diagram (itu-r bt.656 input to dual rgb output) ........ 12 figure 4 S5D2400X system block diagram (itu-r bt.601 input to single rgb output) ..... 13 figure 5 S5D2400X system block diagram (dvi input to single rgb output) ..................... 14 figure 6 S5D2400X functional block diagram ................................ ................................ ..... 15 figure 7 S5D2400X solut ion circuit for application ................................ .............................. 16 figure 8 internal clock system diagram ................................ ................................ ............... 17 figure 10 osd font ram ................................ ................................ ................................ ....... 23 figure 11 osd display ram ................................ ................................ ................................ .. 24 figure 12 osd font structure ................................ ................................ .............................. 26 figure 13 osd display ram structure ................................ ................................ ................... 26 figure 14 osd position ................................ ................................ ................................ .......... 27 figure 15 osd multi color font structure ................................ ................................ .............. 29 figure 16 osd row space ................................ ................................ ................................ ..... 30 figure 17 half tone block ................................ ................................ ................................ ...... 31 figure 18 r-channel gamma correction ................................ ................................ ................ 31 figure 19 error diffusion architecture ................................ ................................ ..................... 32 figure 20 tpg sync signals ................................ ................................ ................................ .. 33 figure 21 test pattern generation method ................................ ................................ ............. 33 figure 22 built-in test patte rns ................................ ................................ .............................. 34
preliminary datasheet S5D2400X 5 1 overview 1.1 overview S5D2400X scaling image processor is a display soc designed for tft-lcd monitors and tv systems. this chip consists of scaler, deinterlace and ace block. the chip receives the signal of digital rgb 24-bit or itu-r bt.656/601 format, deinterlaces the signal and sends the single or dual channel digital data (24-bit or 48-bit). the chip provides the acce (adaptive color & contrast enhancement) function that minimizes color change and improves brightness function, and has the built-in filter that improves sharpness. the built-in osd supports 512 rom fonts of 12*18 matrix, and processes 28 ram fonts. 1.2 applications multimedia lcd monitors/tvs digital tvs crts and rear projection tvs plasma displays projection displays 1.3 features high-quality advanced scaling ? fully programmable scale-up ratios ? scale-up or down for horizontal and vertical built-in osd for lcd monitor ? 512 rom fonts ? 28 ram fonts economic output clock source ? built-in pll core ? external x- tal device supports i 2 c bus host interface r/g/b gamma look-up table dithering ? 8 to 6 dithering
preliminary datasheet S5D2400X 6 color & contrast management ? adaptive contrast control ? adaptive brightness control ? image sharpness control ? color compensation ? boost up sub zone digital rgb input video de-interlacing ? itu-r bt.656 interfacing ? itu-r bt.601 interfacing ? spatial interpolation filter pkg information ? pkg: 100-tqfp-1414 (100tqfp) operating conditions ? 1.8 volts co re ? 3.3 volts i/o
preliminary datasheet S5D2400X 7 2 pin information 2.1 pin configuration S5D2400X tft-lcd image navigator vdd3op bo7 bo6 bo5 bo4 bo3 bo2 bo1 bo0 vss3op go7 go6 go5 go4 go3 go2 go1 go0 vdd2i ro7 ro6 ro5 ro4 ro3 ro2 ro1 ro0 vss2i mifsel i2cen scsn scl sda rstn vdd3op x1 x2 vss3op vssdp vdddp vbbp filt vssap vddap vck vdd2i vi0 vi1 vi2 vi3 bio1 bio0 vss3op gio7 gio6 gio5 gio4 gio3 gio2 gio1 gio0 vdd3op rio7 rio6 rio5 rio4 rio3 rio2 rio1 rio0 vss2i vi7 vi6 vi5 vi4 phso pvso pden pcko tmd1 tmd0 scan dden dcki vss2i dhs dvs fld ghs gvs gpo2 gpo1 gpo0 vdd2i bio7 bio6 bio5 bio4 bio3 bio2 1 100 10 20 25 26 30 40 50 51 60 70 75 76 80 90 figure 1. S5D2400X pin configuration
preliminary datasheet S5D2400X 8 2.2 pin description i/o legend : i = input o = output p = power g = ground table 1. mcu interface pins pin name i/o pin no description mifsel i 4 mcu i/f logic selection (always high) i2cen i 5 i 2 c enable signal (always high) scsn i 6 chip select signal. (always high) scl i 7 serial bus clock sda i/o 8 serial bus data (i: input data, o: output data) gpo0 o 58 general purpose output 0 gpo1 o 59 general purpose output 1 gpo2 o 60 general purpose output 2 table 2. pll interface pins pin name i/o pin no description x1 i 11 x- tal input (max 30 mhz) x2 o 12 x- tal output filt o 17 pll external loop filter (refer to the circuit diagram on page 14.) table 3. video input interface pins pin name i/o pin no description vck i 20 input clock for video mode (de-interlace) vi[7:0] i 22~29 itu-r bt.656: video data input port itu-r bt.601: y data input port pull down by internal 70k w resistors gvs i 61 itu-r bt.601: v-sync input from decoder ghs i 62 itu-r bt.601: h-sync input from decoder fld i 63 itu-r bt.601: external field signal input
preliminary datasheet S5D2400X 9 table 4. dvi interface pins pin name i/o pin no description rstn i 9 system reset (low active) rio[7:0] i/o 31 ~ 38 input or dual output port red[7:0] itu-r bt.601: uv data input port pull down resistors gio[7:0] i/o 40 ~ 47 input or dual output port green[7:0] pull down resistors bio[7:0] i/o 49 ~ 56 input or dual output port blue[7:0] pull down resistors dvs i 64 v-sync input dhs i 65 h-sync input dck i 67 input clock dden i 68 input data enable (digital input mode) table 5. panel interface pins pin name i/o pin no description ro[7:0] o 1~2 95~100 single output port red[7:0] pcko o 72 output clock pden o 73 output data enable pvso o 74 v-sync output phso o 75 h-sync output bo[7:0] o 77~84 single output port blue[7:0] go[7:0] o 86~93 single output port green[7:0] table 6. test pins pin name i/o pin no description scan i 69 scan enable signal for test. not use normal condition (always low) tmd0 i 70 test mode selection 0 (always low) tmd1 i 71 test mode selection 1 (always low)
preliminary datasheet S5D2400X 10 table 7. supply voltage and ground pins: 3.3 / 1.8 volt pin name pin number description vss2i 3, 30, 66 internal ground vdd3op 10, 39, 76 3.3v output-driver and pre-driver supply voltage vss3op 13, 48, 85 output-driver and pre-driver ground vssdp 14 pll digital ground vdddp 15 1.8v pll digital supply voltage vbbp 16 pll bulk-bias ground vssap 18 pll analog ground vddap 19 1.8v pll analog supply voltage vdd2i 21, 57, 94 1.8v internal supply voltage total supply voltage : 8 pin (3.3v: 3 pin, 1.8v: 3 pin, pll (1.8v): 2 pin) ground : 9 pin (3.3v: 3 pin, 1.8v: 3 pin, pll (1.8v): 2 pin, analog (bulk-bias 1.8v): 1 pin)
preliminary datasheet S5D2400X 11 3 functional block diagram 3.1 system block diagram ? ? itu-r bt.656 input to single rgb output system S5D2400X x2 scl sda video input 24 rgb output phso/pvso/ pden/pcko vck vi (itu-r bt.656) 8 x1 x-tal display port 18 lvds or pannel deinterlacer video decoder osc port host i/f port mcu * rgb output 18-bit: ro2 - ro7 go2 - go7 bo2 - bo7 24-bit: ro0 - ro7 go0 - go7 bo0 - bo7 figure 2. S5D2400X system block diagram (itu-r bt.656 input to single rgb output)
preliminary datasheet S5D2400X 12 ? ? itu-r bt.656 input to dual rgb output system S5D2400X x2 scl sda video input 48 rgb output phso/pvso/ pden/pcko vck vi (itu-r bt.656) 8 x1 x-tal display port lvds or pannel deinterlacer video decoder osc port host i/f port mcu * rgb output a channel: ro0 - ro7 go0 - go7 bo0 - bo7 rio0 - rio7 gio0 - gio7 bio0 - bio7 b channel: figure 3. S5D2400X system block diagram (itu-r bt.656 input to dual rgb output)
preliminary datasheet S5D2400X 13 ? ? itu-r bt.601 input to single rgb output system S5D2400X x2 scl sda video input 24 rgb output phso/pvso/ pden/pcko uv x1 x-tal * rgb output display port 18 lvds or pannel 18-bit: ro2 - ro7 go2 - go7 bo2 - bo7 24-bit: ro0 - ro7 go0 - go7 bo0 - bo7 deinterlacer video decoder osc port host i/f port mcu vck/fld gvs/ghs 8 8 y (itu-r bt.601) * uv data input 8-bit: rio0 - rio7 * y data input 8-bit: vi0 - vi7 figure 4. S5D2400X system block diagram (itu-r bt.601 input to single rgb output)
preliminary datasheet S5D2400X 14 ? ? dvi input to single rgb output system S5D2400X x2 scl sda dvi graphic input 24 rgb output phso/pvso/ pden/pcko x1 x-tal * rgb output display port lvds or pannel ro0 - ro7 go0 - go7 bo0 - bo7 tmds osc port host i/f port mcu rgb input 24 * rgb input rio0 - rio7 gio0 - gio7 bio0 - bio7 dck/dden/ dhs/dvs figure 5. S5D2400X system block diagram (dvi input to single rgb output)
preliminary datasheet S5D2400X 15 3.2 functional block diagram hardware reset mifsel i2cen scl sda cki dck video_on int.osc vck x1 x2 cko filt rstn video_on rio7-rio0 gio7-gio0 bio7-bio0 vi7-vi0 itu-r.656 ro7-ro0 go7-go0 bo7-bo0 phso pvso pden pcko osd_on sc_on bu_on ckosc 0 1 input data formatter de- interlacer sfc scaling engine adaptive coeff. gen 0 1 boost-up & sharpness control 0 1 scaling controller contrast control osd mix rgb gamma correction 8 to 6-bit dither output data formatter timing generator 0 1 osd pll ram fonts rom fonts sync delay match host interface figure 6. S5D2400X functional block diagram
preliminary datasheet S5D2400X 16 4 solution circuit for application vdd3op bo7 bo6 bo5 bo4 bo3 bo2 bo1 bo0 vss3op go7 go6 go5 go4 go3 go2 go1 go0 vdd2i ro7 ro6 ro5 ro4 ro3 ro2 ro1 ro0 vss2i mifsel i2cen scsn scl sda rstn vdd3op x1 x2 vss3op vssdp vdddp vbbp filt vssap vddap vck vdd2i vi0 vi1 vi2 vi3 bio1 bio0 vss3op gio7 gio6 gio5 gio4 gio3 gio2 gio1 gio0 vdd3op rio7 rio6 rio5 rio4 rio3 rio2 rio1 rio0 vss2i vi7 vi6 vi5 vi4 phso pvso pden pcko tmd1 tmd0 scan dden dcki vss2i dhs dvs fld ghs gvs gpo2 gpo1 gpo0 vdd2i bio7 bio6 bio5 bio4 bio3 bio2 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 36 35 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 d_gnd +3.3vd2 +1.8vd1 +3.3vd2 3.3k 3.3k 3.3k 100 100 100 scl sda rstn 22pf d_gnd 22pf 1m 25mhz i_video[0...7] o_blue7 o_blue6 o_blue5 o_blue4 o_blue3 o_blue2 o_blue1 o_blue0 o_blue[0...7] o_green[0...7] o_green7 o_green6 o_green5 o_green4 o_green3 o_green2 o_green1 o_green0 o_red[0...7] o_red7 o_red6 o_red5 o_red4 o_red3 o_red2 o_red1 o_red0 i_video7 i_video6 i_video5 i_video4 i_video3 i_video2 i_video1 i_video0 video_clk d_gnd 4.7k 47nf 3.9nf +1.8vp 1.5uh 100nf d_gnd - itu-r bt.656 input port vi[0:7]: video data input port vck: video clock input port. - itu-r bt.601 input port vi[0:7]: v data input port rio[0:7]:uv data input port vck: video clock input port fld: field signal input port ghs: h-sync input port gvs: v-sync input port i/o_red[0...7] i/o_red7 i/o_red6 i/o_red5 i/o_red4 i/o_red3 i/o_red2 i/o_red1 i/o_red0 i/o_green[0...7] i/o_green7 i/o_green6 i/o_green5 i/o_green4 i/o_green3 i/o_green2 i/o_green1 i/o_green0 i/o_blue[0...7] i/o_blue7 i/o_blue6 i/o_blue5 i/o_blue4 i/o_blue3 i/o_blue2 i/o_blue1 i/o_blue0 vsync hsync hsync vsync field clk den out_hs out_vs out_de out_ck dvi-de dvi-ck dvi-hs dvi-vs 601_fld 601-vs 601-hs S5D2400X 100-tqfp-1414 (an) figure 7. S5D2400X solution circuit for application
preliminary datasheet S5D2400X 17 5. functional description 5.1 clock systems and system operation modes 5.1.1 clock systems the chip supports switching of separate-rgb signal or itu-r bt.656/601 protocol video signal data. the separate-rgb data input clock is dck, and the itu-r bt.656/601 format video signal input clock is vck. the external x- tal oscillation clock x1 is a free-run clock (recommended 25mhz) which is used as the source clock of pll in creating data fetch and output clock for host interface. the external clock is created by internal pll based on the x1 frequency input in accordance with the scaling factor, and is sent to the scaling output terminal and the panel display clock (pcko). in other words, the clock system selects dck/vck as the external clock, uses the free-run clock x1 as the source of output clock and for host i/f, and creates the output clock based on the scaling factor in the internal pll. in order to reduce power consumption, it is possible to control the clock system to selectively enable/disable scaler, osd, de- interlacer, boost-up and other blocks. in the dpms mode, input and output clock is disabled, and only the free-run x1 clock is enabled. rio7 - rio0 gio7 - gio0 bio7 - bio0 data-path sfc (sampling freq. conversion) ro7 - ro0 go7 - go0 bo7 - bo0 vi7 - vi0 input domain output domain dck vck x1 x2 cki (input clock) internal oscillator ckosc (free-run clock) cko (output clock) freq. synthesis pcko note: cki, cko, ckosc: internal clock name host i/f & register control pre-divider pll figure 8. internal clock system diagram
preliminary datasheet S5D2400X 18 5.1.2 system operation modes the operation mode is divided, depending on the application system, into separate rgb signal input so that the signal can be used in the flat panel display, and processing of video signal entered to itu-r bt.656/601. the built-in auto tuning function and the de-interlace function may operate against each other. in this way, power consumption can be minimized through management of the functional block . the table below shows the example of on/off operation sets. in the dpms mode, all the functional blocks are off, and only the host interface function works by x- tal clock x1. in the separate rgb input mode, only the basic_on register must be on for simple 1:1 action. it is possible to expand, in the system level, the operation mode set which is not described in the table. mode itu-r bt.656 common remark video_on sc_on bu_on osd_on basic_on dpms (no sync) x x x x x standby (x1 clock) bypass 1 x x x x o sep. rgb (no scale) bypass 2 x x x o o sep. rgb no scale + osd bypass 3 x x o x o sep. rgb no scale + bu scale up/down 1 x o o o o sep. rgb all operation scale up/down 2 o o x o o itu-r bt.656 scale + osd scale up/down 3 o o o x o itu-r bt.656 scale + bu scale up/down 4 o o o o o itu-r bt.656 all operation notes: 1. ref. register map (0x0001[6:0]) 2. "o " ? on (logical "h"), "x" ? off (logical "l") 3. description video_on : de-interlace on / off for itu-r bt.656/601 video mode (separate-rgb or itu-r bt.656/601 mode selection) sc_on : scaler on / off bu_on : boost-up on / off for image enhancement osd_on : on-screen display on / off for user control mode basic_on : basic logic path on / off (always on except dpms mode)
preliminary datasheet S5D2400X 19 5.2 de-interlace the de-interlace block receives the itu-r bt.656/601 format data, and converts the luminance data and chrominance data from interlace scan mode to progressive scan mode. the luminance data and chrominance data in progressive scan are converted into red/green/blue (rgb) data. the itu-r bt.656 format data are separated into horizontal sync, vertical sync, field information, luminance data and chrominance data, and itu-r bt.601 format data are separated into luminance data and chrominance data with horizontal sync, vertical sync and field information received through the other pin. 5.2.1 functions horizontal sync separation from itu-r bt.656 format data vertical sync separation from itu-r bt.656 format data field information separation from itu-r bt.656 format data luminance data separation from itu-r bt.656 format data chrominance data separation from itu-r bt.656 format data interlace to progressive scan conversion for luminance and chrominance data red / green / blue (rgb) data conversion from luminance / cb / cr ( ycbcr) data 5.2.2 itu-r bt.656 format data separation the itu-r bt.656 format data separation block separates horizontal sync, vertical sync, field information, luminance data and chrominance data from the itu-r bt.656 format data input. horizontal sync is in low state in blanking interval, and in high state in active interval. vertical sync is in low state in blanking interval and in high state in active interval. f is in high state in odd field, and in low state in even field. the active data are a set of cb/y/ cr/y. 5.2.3 interlace to progressive scan conversion the interlace to progressive scan conversion (ipc) block converts the field structure of interlace scan into the frame structure of progressive scan. in other words, 60 hz / 30 frame (60 field) interlace scan is changed into 60 hz / 60 frame progressive scan. in interlace to progressive scan conversion, the progressive scan line of 1 frame becomes double of the interlace scan line. in S5D2400X, you can select whether to double the line or maintain the line as it is when converting scan. 5.2.4 ycbcr to rgb conversion the ycbcr to rgb conversion block converts the y / cb / cr data into the red / green / blue data.
preliminary datasheet S5D2400X 20 5.3 timing generator the timing generator makes timing for S5D2400X, and delivers the value required to make pcko (output clock). using the input hs and vs, the block generates phso, pvso and pden for output sync, and the signals made with the optimum timing for each block are sent to other blocks. tg also delivers the value required for pcko. it sends the mcu setting value to internal pll. 5.3.1 output timing generation using input hs and vs, tg generates the output sync (phso, pvso and pden). the active data area must be set in input hs and vs. as shown in the following figure, set hia_str (0x0012, 0x0013), hia_end (0x0014, 0x0015), via_str (0x0016, 0x0017), via_end (0x0018, 0x0019), hias (0x0020, 0x0021) and vias (0x0022, 0x0023). hbp hfp h_active data_area hsw h_input_total h_start_point h_end_point vbp vfp v_active data_area vsw v_input_total v_start_point v_end_point horizontal sync input vertical sync input figure 9 output timing generation the output signal can be set in hofp (0x001a), hosw (0x001b), hobp (0x001c, 0x001d), vofp (0x001e), vosw (0x001f), hoas (0x0024, 0x0025), voas (0x0026, 0x0027).
preliminary datasheet S5D2400X 21 5.4 scaler the scaler of S5D2400X operates in the following three modes (scale-up, scale-down, bypass). 5.4.1 scale-up the scaler can perform scale-up from vga to xga (vga ? svga, vga ? xga, svga ? xga) in the dvi mode, and from vga to 100mhz (vga ? svga, vga ? xga, vga ? 100 mhz, svga ? xga, svga ? 100 mhz, xga ? 100 mhz) in the itu-r bt.656/601 mode. different scaling ratio may be applied to h/v (horizontal/vertical) direction. 5.4.2 scale-down the scaler can perform scale-down from xga to vga (xga ? svga, xga ? vga, svga ? vga), and different scaling ratio may be applied to h/v directions. 5.4.3 bypass in the bypass mode, the ratio between input and output image is 1:1. in this case, power consumption is decreased if the scaler is off (0x001[1]). the bypass mode can be used together with the scale-up mode. in order to use the two modes together, set bypass (1:1) to horizontal direction and scale-up (vgp ? xga) to the vertical direction. 5.5 boost-up the boost-up block provides you a clear screen. 5.5.1 adaptive contrast control this function provides a clearer view of a part of or the entire screen by sorting the color to find the maximum, minimum and average value and perform the contrast control processing, and replacing the color with the adaptively calculated color. 5.5.2 adaptive brightness control this function provides a brighter screen based on a given lut value. lut is 0 ~ 255, and is mapping by 1:1. 5.5.3 image sharpness control the image sharpness control processing provides a more distinctive view of each color by increasing sharpness of boundary of each color. 5.5.4 color compensation a color can be distorted on the screen and may look like a completely different color. the color compensation circuit corrects this problem and maintains the original color. 5.5.5 boost up sub zone boost up function recognizes the current status of the screen, and reflects the result on the screen. the screen area to be recognized is called "sub zone". setting the sub zone is necessary because the screen may be affected by other data than the actual video image.
preliminary datasheet S5D2400X 22 5.6 osd (on-screen display) osd function provides outward gui between tft_lcd monitor and end-user, enabling the user to easily control the environment of tft-lcd monitor. osd supports up to 512 rom fonts; 16 mcf (multi-colored font) and 464 sf (standard font). osd can be set on certain area of the screen with certain size. 5.6.1 osd fonts 1) rom font 7 languages 464 standard fonts (sf) 16 multi-colored font (mcf) 2) ram font user definable font max. 28 sf, max. 9 mcf
preliminary datasheet S5D2400X 23 3) font ram structure font ram is assigned of 1008 addresses (from 0x3fff to 0x43ee). where, 1008 is (8 row * 28 fonts) * 2 = 504 * 2. 1008/28 = 36, and therefore, 36 addresses are assigned to a font. because the host interface transports data in the unit of 8 bits, in order to configure a font of 12*18 as shown in figure 10, the upper 4 bits and the lower 8 bits of 1line (12 bits) are assigned as an address. the upper 4 bits are transported as the even address and the lower 8 bits are transported as the odd address to font ram, respectively. x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0x3fff 0x4000 0x4001 0x4002 0x4003 0x4004 0x4005 0x4006 0x4007 0x4008 0x4009 0x400a 0x400b 0x400c 0x400d 0x400e 0x400f 0x4010 0x4011 0x4012 0x4013 0x4014 0x4015 0x4016 0x4017 0x4018 0x4019 0x401a 0x401b 0x401c 0x401d 0x401e 0x401f 0x4020 0x4021 0x4022 even address 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 font ram odd address x x x x x x x x x x x x figure 10. osd font ram
preliminary datasheet S5D2400X 24 4) display ram structure display ram is assigned of 900 addresses (0x2000 ~ 0x2383). as 900/450 = 2, 2 addresses are assigned to a display ram cell. because the host interface transports data in the unit of 8 bits, in order to form the display ram cell that uses 16 bits as a cell, 2 addresses must be transported. figure 11 shows the structure of display ram cell. 0 1 2 3 27 18 12 0x2000 0x2001 0x2002 0x2003 0x2004 0x2005 0x2006 0x2007 0x2008 0x2009 0x200a 0x200b 0x200c 0x200d 0x200e 0x200f 0x2010 0x2011 0x2012 0x2013 ... 0x2382 0x2383 font number display ram font ram a b c & 3 2 3 0 5 13 11 10 27 15 . . . 1 boder/ shadow blink font color (fc) font number display ram cell ram/rom select even address odd address figure 11. osd display ram
preliminary datasheet S5D2400X 25 5) font ram clear this function clears the font ram based on rising edge detect. the font ram is cleared by power on reset or ftram_clrn register. the operation time is 1 clock, and no delay is made. the refresh region indicates that "0" value will be given to the entire memory. down load or clear works only when osd_on register is on. in basic operation the font ram clear function is not required. using the function in basic mode may cause data loss or other critical problems. 6) display ram clear this function clears display ram based on the rising edge detect. the ram is cleared by power on reset or dsram_clrn register. the operation time is 1 clock, and no delay is made. 5.6.2 osd windows 1. flexible osd size: displays up to 64 fonts in horizontal within the range of 450 fonts displays up to 64 fonts in vertical within the range of 450 fonts 2. up to 4 multiple windows (1 main window + 4 multiple windows) 3. up to 32 windows color including intensity 4. programmable multiple windows shadow color/size 5. fine windows bordering 6. pop up / down-able multiple windows 7. font position mapping based multiple windows horizontal/vertical start / end point adjustment 8. transparency: input image / osd image mix.
preliminary datasheet S5D2400X 26 5.6.3 system description osd stores rom and font ram address and features on the display ram, displays the font and its features at the designated position, and displays on the screen the features designated in osd register. 1) font osd font consists of 12 18 (width length) pixels, and is divided into character and raster when displayed on the screen. font 12 18 raster character a figure 12. osd font structure font color can be controlled by fc of display ram. each font can have 16 character colors and 16 raster colors. fc value is used as a reference of lut to control character color and raster color. 2) user definable osd area osd area is defined with the number of osd horizontal fonts and the number of osd vertical fonts to be displayed on the screen by osd_hfont[5:0] and osd_vfont[5:0]. osd_hfont and osd_vfont are assigned of 6 bits each, generating 64 horizontal/vertical fonts respectively. because the maximum size of display ram is limited to 450, it must meet osd_hfont*osd_vfont 450. (ram address 0 ~ 449) if osd_hfont is set to 30 and osd_vfont to 10, osd area is displayed as shown below. in this case, addresses 0~299 of the display ram are used for display. 1 display ram address 0 1 a l p h a 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 2 3 4 5 6 7 8 9 10 display ram address 30 figure 13. osd display ram structure
preliminary datasheet S5D2400X 27 5.6.4. functions 1) osd position start position of osd can be changed via osd_hsp and osd_vsp of the osd register. (osd_hsp, osd_vsp) horizontal active area vertical active area osd window border component (luo, lui, rli, rlo, tk, tn) (1, 1) luo lui rlo rli tk tn osd area figure 14. osd position 2) font size control osd fonts are saved in fontram or rom in the unit of 12 bits, displayed as a 12*18 font through no. 18 access and display. the horizontal and vertical size of a font can be 1x, 2x, 3x and 4x through adjustment of ch_hsz and ch_vsz. 3) character border/shadow character border/shadow of a font can be implemented through ch_bdsh_en setting in osd register, and with 1or 0 (1: border, 0: shadow) selection of ch_bdsh of display ram. 4) blink control osd blink can be controlled by font. font blinking function is enabled through bl_ntra ( blink or notoneraster) setting and display ram blink setting. blnk_sel is used to adjust blink duty as the blink function is enabled.
preliminary datasheet S5D2400X 28 blnk_sel blink off blink on 0 0.5 sec 0.5 sec 1 1 sec 0.5 sec 2 0.5 sec 1 sec 3 1 sec 1 sec 4 1.5 sec 1.5 sec 5 2 sec 1 sec 6 1 sec 2 sec 7 2 sec 2 sec blnk_c supports the color inversion of the blinking character. if blnk_c is enabled, the complementary color of the font raster color is displayed in the character area during blink-off. if blink_c is reset, the raster color is displayed in the character area during blink-off. 5) intensity control osd intensity can be controlled by frame. it is possible to control 16 colors by character / raster in reference to lut of display ram fc (font color), or 32 colors by frame by toggling intensity bit. 6) multi-colored font control osd provides 512 rom fonts to display the icon, generating multi-language osd icon. out of 512 rom fonts, 464 fonts are the standard fonts (single-color) and 16 (16*3 = 48) fonts are multi-colored fonts. each multi- colored font consists of three color attribute rom fonts. the three fonts make a multi-colored font with or operation. in order to access a multi-colored font, the r-color attribute font is addressed. for example, 1d0h, 1e0h and 1f0h address indicate r, g and b-color attribute fonts respectively. by addressing 1d0h, a multi- colored font can be accessed through or operation of 1d0h, 1e0h and 1f0h color attribute fonts.
preliminary datasheet S5D2400X 29 1 0 1f0h : blue 1e0h : green 1d0h : red masked data of multi-color font: 1d0h displayed font: 1d0h r y g c b figure 15. osd multi color font structure the multi-colored font (mcf) of the ram font is made in the same way as the standard font (sf) is formed. mcf count can be adjusted through the n_mcf value, and 28 fonts except mcf are used as sf. 7) external osd control if the external osd is enabled (ext_osd_sel == 1), the external osd expresses the color in reference to lut of S5D2400X_osd. for color mapping, refer to 4-3. receiving r, g, b, i, en input from the external osd, S5D2400X_osd decodes the 4 inputs except en, and displays each color value. external osd input is delayed by 2pixel clock before displayed. even if external osd is used, S5D2400X_osd supports half tone. in order to apply half tone to font raster and not to apply half tone to the character, the values between 0000b and 1011b shall be assigned to r, g, b, i. (osd_tone == 0, ch_tone == 0)
preliminary datasheet S5D2400X 30 8) blank font control by accessing and displaying 000h address of rom, it is possible to display only input image within the osd area. this rom 000h address called a blank font has several useful functions. for example, multiple windows can be displayed on the osd area only. the function can be used to display multiple windows without the osd area. 9) row space a row space indicates the space in vertical direction between the fonts displayed on osd. S5D2400X_osd assigns 0-15 to row_sp to implement the row space. a row space is displayed on the screen via interworking with character vertical size (ch_vsz). in other words, if ch_vsz is 1 and row_sp is 3, the row space actually displayed is 6 pixels. the maximum number of vertical pixels of a row space to be displayed is 4*15 (ch_vsz == 3, when row_sp == 15). if row space is enabled, the raster is extended as many as the row space pixels on the top or bottom of a font. figure 18 shows the details. (when row_sp == 1, and ch_vsz == 0). if row space is applied, the multi color ram font has extended row on the top and bottom of the font. row space a b 18 18 20 row space figure 16. osd row space
preliminary datasheet S5D2400X 31 10) half tone (transparency) control half tone of S5D2400X_osd is made via mixing of input image and osd image. where, osd_tone[1:0] is used as a weight for mixing of image and osd image. input image osd image half tone image 1-w w figure 17. half tone block 5.7 gamma the gamma correction block performs gamma compensation to complement the tft-lcd panel features. the block divides the input signal level to various sections, makes non-linear feature curve for each section, and by linear interpolation of each section, performs gamma compensation. in other words, the block divides the input into sections, and changes the output value of each section to deform specific curves for gamma compensation. an input signal has 8 bits digital level, it is evenly divided into 32 sections with the space of 8. the block receives output value for each evenly spaced level from mcu, performs non-linear gamma compensation, and performs linear interpolation for the values between the levels. gamma compensation is applied to each of rgb data in the same way, but the output values can be changed respectively. 0 ryav1 ryav2 ryav3 ryav4 ryav30 ryav31 ryav32 x y 8 16 24 32 . . . . 240, 248, 255, figure 18. r-channel gamma correction
preliminary datasheet S5D2400X 32 5.8 contrast control contrast block is applied to all pixels, and can control the boost-up area and other areas respectively. blacklevel and brightness play the role of offset, and contrast works as gain. each pixel value is acquired in the following process. rout = [ rin - blacklevel(red)] * contrast(red) + brightness(red) gout = [gin - blacklevel(green)] * contrast(green) + brightness(green) bout = [bin - blacklevel(blue)] * contrast(blue) + brightness(blue) 5.9 dither 5.9.1 enable dither the dithering block supports the following 4 modes. table 8. dither mode dth_mode[1:0] operation mode (i/o and rgb data valid bit count) 000 bypass mode (8-bit rgb input, 8-bit rgb output) 101 ed mode (8-bit rgb input, 6-bit rgb output) 5.9.2 error diffusion (ed) method the following figure illustrates the block diagram of error diffusion dithering. the block diagram is made for r, but can be applied to g and b in the same manner. r r_d threshold error filter figure 19. error diffusion architecture the threshold block cuts off the lower 2 bits. therefore the cut 2 bits are used as the input to the error filter.
preliminary datasheet S5D2400X 33 5.10 test pattern generator (tpg) tpg internally generates a pattern for sync and test without input sync and data. in order to enable tpg, test_pat_on (0x0001[7]) must be high. 5.10.1 tpg sync signals figure 20 illustrates the internally generated sync. hs active data area vs active line area 3 16 1 16 64 120 figure 20. tpg sync signals the active data area and the active line area in figure 20 are determined by tp_resolution (0x0006 [7:6]). table 9. active pattern areas pattern_size 0 1 2 active area (h*v) vga (640*480) svga (800*600) xga (1024*768) 5.10.2 test patterns the pattern to be used as input data to scaler is selected by tp_type(0x0006[5:0]). for bit [5], 0 is pass and 1 inverts image. for bit [4], 0 sends normal pattern and 1 sends h/v ramp waveform. other bits are described in figure 21.(a) and (b). figure 21.(a) illustrates the ramp waveform selection in h/v direction when bit [4] is 1. figure 22 (a) shows the example. figure 21.(b) shows the example when bit [4] is 0. if the lower 4bits are 0~5, the screen pattern is as displayed in figure 22.(b). the other values from 6~15 display the white screen. inv. pattern index 0 0 - 5 [5] [4] [3] [2] [1] [0] inv. h/v sel 0~7:ramp wavelength interval 1 [5] [4] [3] [2] [1] [0] (a) (b) figure 21. test pattern generation method
preliminary datasheet S5D2400X 34 1 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 0 1 0 1 1 0 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 1 0 0 0 1 (a) 0 : boundary 5 : black 1 : diagonal ramp 2 : on/off 4 : v-line 3 : h-line (b) figure 22. built-in test patterns
preliminary datasheet S5D2400X 35 5.11 i2c host interface protocol S5D2400X supports data communication through i2c protocol based host interface. the slave address for a device id is 7 bits (binary "0000101"). the address is made with 15 bits with 8 bits data depth. therefore, in order to access an address, 2 bytes (address msb, address lsb) are indexed with 1 byte data depth. because the address bits are 15 bits, the 1 byte of the address msb is binary "x a 14 a 13 a 12 a 11 a 10 a 9 a 8 ", and the 1 byte of the address lsb is binary "a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 ". 5.11.1 timing chart (data sequence for register write/read of n registers) write data sequence w start ack ack sda scl device id address msb ack ack sda scl address lsb data 1 stop sda scl data 2 data n ack read data sequence r start ack ack sda scl device id address msb ack ack sda scl address lsb data 1 stop ack sda scl data 2 data n the figure below shows the device id and read/write byte for the slave address in the above timing chart.
preliminary datasheet S5D2400X 36 device id 0 0 0 0 1 0 1 r/ w (r = 1, w = 0) because an address is 15 bits, the 1 bit of the address msb is remained. set 0 or 1 (don't care : x) for the 1 bit. 5.11.2 example write to one register send start signal send device id byte (r/ w bit = low) send address msb send address lsb send data to address send stop signal write to four consecutive register send start signal send device id byte (r/ w bit = low) send address msb send address lsb send data 1 to address send data 2 to (address + 1) send data 3 to (address + 2) send data 4 to (address + 3) send stop signal read from one register send start signal send device id byte (r/ w bit = high) send address msb send address lsb receive data from address send stop signal
preliminary datasheet S5D2400X 37 read form four consecutive control registers send start signal send device id byte (r/ w bit = high) send address msb send address lsb receive data 1 from ad dress receive data 2 from (address + 1) receive data 3 from (address + 2) receive data 4 from (address + 3) send stop signal
preliminary datasheet S5D2400X 38 6 register map 6.1 global control registers bits register name function 0x0000 global_reset (default: 0 x 01) r/w 7:2 reserved 1 free_run pseudo sync run mode (1: on, 0: off (default)) - when to use : power on, mode switch, and recovery from over sync/under sync dpms 0 soft_rstn resets the chip in software level except user register (the register defined in the spec data sheet). (low active) - when to use: power on and mode switch - how to use: set the chip to 0, reset, and then to 1. (reset time must be 1us or higher (1 clock) without delay.) the last "n" of the register name indicates active low soft reset. 0x0001 global_block_control (default: 0 x 03) r/w 7 test_pat_on blocks input regardless of external data input status, and displays the internal test pattern. test pattern (1: on, 0: off (default)) 6 video_on video mode & dvi mode (1: video mode, 0: dvi mode (default)) 5 reserved 4 bu_on boost up (1: on, 0: off (default)). do not use in the dvi mode. 3 osd_on osd (1: on, 0: off (default)) 2 reserved 1 sc_on - up to 10x for scaling-up and up to 1/2x for scaling-down - the screen size is not changed when switching off sc_on when the target resolution and the input resolution are the same (1x scaling). - in bypass status, only scaling is bypassed. therefore, pms setting must be performed. (1: scaler on, 0: scaler off (default)) 0 basic_on in the normal operation status, basic logic must be always on. (1: basic logic on (default), 0: basic logic off)
preliminary datasheet S5D2400X 39 0x0002 global_io_control (default: 0 x 00) r/w 7:4 reserved 3 pwm1_on pulse width modulation1 1: on (pwm_data1(0x000d 7:0h) signal is sent through gp01 pin) 0: off(gpo1(ox000b 1h) signal is sent through gp01 pin) 2 pwm0_on pulse width modulation0 1: on (pwm_data0 (0x000c 7:0h) signal is sent through gpo0 pin) 0: off(gpo0(0x000b 0h) signal is sent through gpo0 pin) 1 reserved 0 pll_pwr_save scaler pll power down mode for system clk generation (cko) (1: pll power down mode, 0: normal mode) 0x0003 global_output_control (default: 0 x 38) r/w 7:6 reserved 5 rout_en ro (r-channel output) enable of pin no 1~2, 95~100 rout (1: enable (default), 0: disable) 4 gout_en go (g-channel output) enable of pin no 86~93 gout (1: enable (default), 0: disable) 3 bout_en bo (b-channel output) enable of pin no 77~84 bout (1: enable (default), 0: disable) 2 rin/out_en determines whether to use rio of pin no 31~38 as output or input. if the ochmd bit is 0, rio is used as input regardless of rin/out_en bit control. if the ochmo bit is 1, rio is used as input or output depending on rin/out_en bit control. (1: output, 0: input (default)) 1 gin/out_en determines whether to use gio of pin no 40~47 as output or input if the ochmd bit is 0, gio is used as input regardless of gin/out_en bit control. if the ochmo bit is 1, gio is used as input or output depending on gin/out_en bit control. (1: output, 0: input (default)) 0 bin/out_en determines whether to use bio of pin no 49~56 as output or input. if the ochmd bit is 0, bio is used as input regardless of bin/out_en bit control. if the ochmo bit is 1, bio is used as input or output depending on bin/out_en bit control. (1: output, 0: input (default))
preliminary datasheet S5D2400X 40 0x0004 global_phase_control ((default: 0 x 00) r/w 7:6 reserved 5 cki2_phase changeable 2-times input clock phase (1: phase inverse, 0: normal) 4:0 reserved 0x0005 global_cko_control (default: 0 x 00) r/w 7:6 reserved 5:4 cko_sel cko clock source select (always 00) (00: pll output is used 01,10,11: not used) 3 cko2_phase changeable 2-times scaler output clock phase (1: phase reverse, 0: normal) 2:0 pcko_phase scaler output clock(pcko) time delay - pcko_phase[2] : pcko phase inverse. - pcko_phase[1:0] : x ns delay (x = pcko_phase[1:0]) 0x0006 global_pattern_control (default: 0 x 80) r/w 7:6 pattern_size pattern size select (00: vga, 01: svga, 10: xga (default), 11: unused) 5:0 pattern_sel selecting test pattern type (default: 0) 0x0007 global_position_control (default: 0 x 00) r/w 7:0 must be 08h 0x000a global_io_mode_define (default: 0 x 00) r/w 7:5 dither_mode selecting dither mode type to change from 8 bits to 6 bits on the scaler out. 000 : bypass 101 : error diffusion other values should not be used. 4:3 reserved 2 ichmd scaler input channel mode ( 0: single input (always low)) 1 ochmd scaler output channel mode select (1: dual output, 0: single output) 0 ochsel select a or b channel from scaler output dual channel. - this bit is enabled when addr (0x000a[1]) is dual. 0: in the dual mode, data are sent from channel a. 1: in the dual mode, data are sent from channel b.
preliminary datasheet S5D2400X 41 0x000b global_gpo_data (default: 0 x 00) r/w 7:6 pwm_pre_ scale when pulse width modulation is used, this bit determines, based on the oscillation clock, the level of pwm duty level to be divided. (00: oscillation, 01: 2_divided, 10: 4_divided, 11: 8_divided) 5 pwm_en pulse width modulation enable (1: enable, 0: disable) 4:3 reserved 2 gpo2 general purpose output 2 1 gpo1 general purpose output 1 0 gpo0 general purpose output 0 0x000c global_pwm_data1 (default: 0 x 00) r/w 7:0 pwm_data0 pulse width modulation 0. controls duty in the high section. 0x000d global_pwm_data2 (default: 0 x 00) r/w 7:0 pwm_data1 pulse width modulation1. controls duty in the high section.
preliminary datasheet S5D2400X 42 6.2 timing generator control registers bits register name function 0x0010 tg_mode_sel (default: 0 x 18) r/w 7 hvso_det_on must be always 1. if the bit is "0", hvso_det is not controlled. 6 hvso_det - in invert, the bit initializes tg sync, and detects again to create output sync. event driven phso and pvso detect (low to high, high to low) by write value change operation 5 reserved 4:3 det_frame tg detection start frame (1 ~ 4 frame): (default: 3) : the number of frames required to detect sync after the hvso_det value is changed. 2 prediv_cksel pre-divider clock select (1: cki, 0: ckosc (x1, default)) 1:0 pll_fin_sel pll fin signal select (0: pre_ck ? xga (default), 1: not used, 2, 3: hs ? when scaling rate is small) if hs is used in mcu control, select pre_ck to stabilize clk, and then, select hs. 0x0012 tg_hia_str_h (default: 0 x 01) r/w 7:3 reserved 2:0 hia_str[10:8] manual horizontal input active start point (horizontal input sync width + back porch) 0x0013 tg_hia_str_l (default: 0 x 10) r/w 7:0 hia_str[7:0] manual horizontal input active start point 0x0014 tg_hia_end_h (default: 0 x 05) r/w 7:3 reserved 2:0 hia_end[10:8] manual horizontal input active end point (horizontal input sync width + back porch + active size)
preliminary datasheet S5D2400X 43 0x0015 tg_hia_end_l (default: 0 x 0f) r/w 7:0 hia_end[7:0] manual horizontal input active end point 0x0016 tg_via_str_h (default: 0 x 00) r/w 7:3 reserved 2:0 via_str[10:8] manual vertical input active start point (vertical input sync width + back porch) 0x0017 tg_via_str_l (default: 0 x 1f) r/w 7:0 via_str[7:0] manual vertical input active start point 0x0018 tg_via_end_h (default: 0 x 03) r/w 7:3 reserved 2:0 via_end[10:8] manual vertical input active end point (vertical input sync width + back porch + active size) 0x0019 tg_via_end_l (default: 0 x 1e) r/w 7:0 via_end[7:0] manual vertical input active end point - h/ v_start/end point is changed when via_end[7:0] is controlled. 0x001a tg_hofp (default: 0 x 10) r/w 7:0 hofp horizontal output front porch 0x001b tg_hosw (default: 0 x 60) r/w 7:0 hosw horizontal output sync width 0x001c tg_hobp_h (default: 0 x 00) r/w 7:3 reserved 2:0 hobp[10:8] horizontal output back porch 0x001d tg_hobp_l (default: 0 x b0) r/w 7:0 hobp[7:0] horizontal output back porch
preliminary datasheet S5D2400X 44 0x001e tg_vofp (default: 0 x 01) r/w 7 reserved 6:0 vofp vertical output front porch 0x001f tg_vosw (default: 0 x 03) r/w 7:0 vosw vertical output sync width 0x0020 tg_hias_h (default: 0 x 04) r/w 7:3 reserved 2:0 hias[10:8] horizontal input active size 0x0021 tg_hias_l (default: 0 x 00) r/w 7:0 hias[7:0] horizontal input active size 0x0022 tg_vias_h (default: 0 x 03) r/w 7:3 reserved 2:0 vias[10:8] vertical input active size 0x0023 tg_vias_l (default: 0 x 00) r/w 7:0 vias[7:0] vertical input active size 0x0024 tg_hoas_h (default: 0 x 04) r/w 7:3 reserved 2:0 hoas[10:8] horizontal output active size 0x0025 tg_hoas_l (default: 0 x 00) r/w 7:0 hoas[7:0] horizontal output active size 0x0026 tg_voas_h (default: 0 x 03) r/w 7:3 reserved 2:0 voas[10:8] vertical output active size
preliminary datasheet S5D2400X 45 0x0027 tg_voas_l (default: 0 x 00) r/w 7:0 voas[7:0] vertical output active size 0x0028 tg_pll_p_h (default: 0 x 03) r/w 7:0 pll_p[15:8] pll programmable pre-divider 0x0029 tg_pll_p_l (default: 0 x e8) r/w 7:0 pll_p[7:0] pll programmable pre-divider 0x002a tg_pll_m_h (default: 0 x 18) r/w 7:6 reserved 5:0 pll_m[13:8] pll programmable main-divider 0x002b tg_pll_m_l (default: 0 x 9b) r/w 7:0 pll_m[7:0] pll programmable main-divider 0x002c tg_pll_s (default: 0 x 01) r/w 7:2 reserved 1:0 pll_s pll programmable post scaler 0x002d tg_pll_m_fract (default: 0 x 00) r/w 7:0 pll_m_fract tg's pll_m register fraction bits 0x0032 tg_a_hacto_offset_h (default: 0 x 02) r/w 7:6 reserved 5:0 a_hacto_offset [13:8] automatic horizontal output active point offset delay - up mode: a_hacto_offset = hitotal * vstr_offset * vratio * htotratio / 32 - down mode: a_hacto_offset = 29 * htotratio * vratio + hitotal * vstr_offset * vratio * htotratio/32 ? 2
preliminary datasheet S5D2400X 46 0x0033 tg_a_hacto_offset_l (default: 0 x 90) r/w 7:0 a_hacto_offset [7:0] automatic horizontal output active point offset delay 0x01bo tg_sync_dvi (default: 0 x 0a) r/w 7:5 reserved 4 d_stop_size size detection update enable (1: previous frame data, 0: frame update) 3 dhs_pol_sel tmds output dhs polarity detection priority (1: mcu detection, 0: internal detection) 2 dhs_pol_ext tmds output dhs polarity selection by mcu (dhs_pol_sel = 1) (1: positive type, 0: negative type) 1 dvs_pol_sel tmds output dvs polarity detection priority (1: mcu detection, 0: internal detection) 0 dvs_pol_ext tmds output dvs polarity selection by mcu (dvs_pol_sel = 1) (1: positive type, 0: negative type) 0x01b2 tg_dhs_total_h ro 7:3 reserved 2:0 dhs_hits[10:8] dhs horizontal input total size 0x01b3 tg_dhs_total_l ro 7:0 dhs_hits[7:0] dhs horizontal input total size 0x01b4 tg_dvs_total_h ro 7:3 reserved 2:0 dvs_vits[10:8] dvs vertical input total size 0x01b5 tg_dvs_total_l ro 7:0 dvs_vits[7:0] dvs vertical input total size
preliminary datasheet S5D2400X 47 0x01b6 tg_dden_hia_str_h ro 7:3 reserved 2:0 dd_hia_str[10:8] dden horizontal input active start point 0x01b7 tg_dden_hia_str_l ro 7:0 dd_hia_str[7:0] dden horizontal input active start point 0x01b8 tg_dden_hia_end_h ro 7:3 reserved 2:0 dd_hia_end[10:8] dden horizontal input active end point 0x01b9 tg_dden_hia_end_l ro 7:0 dd_hia_end[7:0] dden horizontal input active end point 0x01ba tg_dden_via_str_h ro 7:3 reserved 2:0 dd_via_str[10:8] dden vertical input active start point 0x01bb tg_dden_via_str_h ro 7:0 dd_via_str[7:0] dden vertical input active start point 0x01bc tg_dden_via_end_h ro 7:3 reserved 2:0 dd_via_end[10:8] dden vertical input active end point 0x01bd tg_dden_via_end_l ro 7:0 dd_via_end[7:0] dden vertical input active end point
preliminary datasheet S5D2400X 48 6.3 de-interlace control registers bits register name function 0x0040 di_ sync_define (default: 0 x 38) r/w 7:6 reserved 5 di_field_pol field signal polarity 1: odd field (field 1) high, even field (field 2) low - required design 0: even field (field 2) high, odd field (field 1) low - 656 spec 4 di_hact_pol hact signal polarity 1: active high - required design 0: active low - 656 spec 3 di_vact_pol vact signal polarity 1: active high - required design 0: active low - 656 spec 2 di_sync_gen sync generation block selection 0: required design 1 di_c_sign chroma sign bit determination 1: 2's complementary - non spec 0: positive number - spec (required design) 0 di_cbcr_sel cb / cr signal input type selection 1: cr y cb y cr y ... - non_spec 0: cb y cr y cb y ... - spec (required design) 0x0041 di_sync_polarity (default: 0 x 00) r/w 7 reserved 6 itu-r bt.656 1: itu-r bt.601, 0: itu-r bt.656 5 di_half_rate 1: half_rate on, 0: half_rate off 4 half_yc_pol_inv half_rate y/c polarity inversion 3 half_vs_pol_inv half_rate v-sync polarity inversion 2 half_hs_pol_inv half_rate h-sync polarity inversion 1 half_hacto_pol_ inv half_rate hacto polarity inversion 0 half_field_pol_ inv half_rate field polarity inversion
preliminary datasheet S5D2400X 49 0x0042 di_vso_sel (default: 0 x 00) r/w 7:4 vso_odd_sel odd field v-sync select 3:0 vso_even_sel even field v-sync select 0x0043 di_hofp (default: 0 x 0a) r/w 7:0 di_hofp horizontal output front porch 0x0044 di_hosw (default: 0 x 1e) r/w 7:0 di_hosw horizontal output sync width 0x0045 di_vofp (default: 0 x 04) r/w 7:0 di_vofp vertical output front porch 0x0046 di_vosw (default: 0 x 06) r/w 7:0 di_vosw vertical output sync width 0x0047 di_line_start (default: 0 x 03) r/w 7:0 di_line_start vertical line start point included active vertical area 0x0048 di_line_width_h (default: 0 x 01) r/w 7:2 reserved 1:0 di_line_width[9:8] vertical line width included active vertical area 0x0049 di_line_width_l (default: 0 x e2) r/w 7:0 di_line_width[7:0] vertical line width included active vertical area 0x004a di_deinterlace_type (default: 0x 0f) r/w 7:4 reserved 3:2 di_di_ytype y interpolation type (trade off of screen blurring and zagging) 0 : screen blurring < -- > 3 : noise 0 : strong zagging < -- > 3 : weak zagging recommended value : 1 1:0 di_di_ctype c interpolation type (the same value with y interpolation type)
preliminary datasheet S5D2400X 50 0x004b di_hacto_mg (default: 0 x ff) r/w 7:4 di_hacto_st_mg hacto signal start point margin (-8 ~ +7) : di_min_h = hacto start + di_hacto_st_mg 3:0 di_hacto_ed_mg hacto signal end point margin (-8 ~ +7) : di_max_h = hacto end + di_hacto_ed_mg 0x004c di_601clk_phase (default: 0 x 00) r/w 7:3 unused 2:0 dclk_phase itu-r bt.601 format clock phase 0x004d di_601hv_sel (default: 0 x 00) r/w 7 unused 6 ext_fld_sel 1: external field select, 0: internal field select 5 hs601_inv itu-r bt.601 h-sync inversion 4 vs601_inv itu-r bt.601 v-sync inversion 3:2 v601_odd itu-r bt.601 odd field active line select 1:0 v601_even itu-r bt.601 even field active line select 0x004e di_601hia_str_h (default: 0 x 00) r/w 7:1 unused 0 di_601hia_str[8] itu-r bt.601 horizontal input active start point 0x004f di_601hia_str_l (default: 0 x ef) r/w 7:0 di_601hia_str[7:0] itu-r bt.601 horizontal input active start point 0x0050 di_601via_str (default: 0 x 11) r/w 7:0 di_601via_str itu-r bt.601 vertical input active start point 0x0051 di_601_vias_h (default: 0 x 00) r/w 7:2 unused 1:0 di_601_vias[9:8] itu-r bt.601 vertical input active size
preliminary datasheet S5D2400X 51 0x0052 di_601_vias_l (default: 0 x f1) r/w 7:0 di_601_vias[7:0] itu-r bt.601 vertical input active size 0x0053 di_field601_th (default: 0 x 46) r/w 7:0 field601_th itu-r bt.601 internal field threshold 0x01c0 di_h_total_h ro 7:3 reserved 2:0 di_hots[10:8] horizontal output total size 0x01c1 di_h_total_l ro 7:0 di_hots[7:0] horizontal output total size 0x01c2 di_v_total_h ro 7:3 reserved 2:0 di_vots[10:8] vertical output total size 0x01c3 di_v_total_l ro 7:0 di_vots[7:0] vertical output total size 0x01c4 di_hoa_str_h ro 7:3 reserved 2:0 di_hoa_str[10:8] horizontal output active start point 0x01c5 di_ hoa_str _l ro 7:0 di_hoa_str[7:0] horizontal output active start point 0x01c6 di_hoa_end_h ro 7:3 reserved 2:0 di_hoa_end[10:8] horizontal output active end point 0x01c7 di_hoa_end_l ro 7:0 di_hoa_end[7:0] horizontal output active end point
preliminary datasheet S5D2400X 52 0x01c8 di_voa_str_h ro 7:3 reserved 2:0 di_voa_str[10:8] vertical output active start point 0x01c9 di_voa_str_l ro 7:0 di_voa_str[7:0] vertical output active start point 0x01ca di_voa_end_h ro 7:3 reserved 2:0 di_voa_end[10:8] vertical output active end point 0x01cb di_voa_end_l ro 7:0 di_voa_end[7:0] vertical output active end point
preliminary datasheet S5D2400X 53 6.4 image scaling control registers bits register name function 0x0061 scaler_ivzoom_h (default: 0 x 02) r/w 7:4 reserved 3:0 ivzoom[19:16] inversed vertical zoom ratio ( = vias/voas ) 0x0062 scaler_ivzoom_m (default: 0 x 00) r/w 7:0 ivzoom[15:8] inversed vertical zoom ratio ( = vias/voas ) 0x0063 scaler_ivzoom_l (default: 0 x 00) r/w 7:0 ivzoom[7:0] inversed vertical zoom ratio ( = vias/voas ) 0x0065 scaler_ihzoom_h (default: 0 x 02) r/w 7:4 reserved 3:0 ihzoom[19:16] inversed horizontal zoom ratio ( = hias/hoas ) 0x0066 scaler_ihzoom_m (default: 0 x 00) r/w 7:0 ihzoom[15:8] inversed horizontal zoom ratio ( = hias/hoas ) 0x0067 scaler_ihzoom_l (default: 0 x 00) r/w 7:0 ihzoom[7:0] inversed horizontal zoom ratio ( = hias/hoas ) 0x0068 scaler_hstr_offset (default: 0 x 00) r/w 7:6 reserved 5:0 hstr_offset sub-pixel horizontal starting point offset for scaling - for scale down : hstr_offset = [ (hias-1) ? (hoas ? 1) / hratio ] * 16 - for scale up : hstr_offset = 32 ? [16 * {(2 * 3*hoas/hias + hoas ? 1) / hratio ? hias ? 1}] %32
preliminary datasheet S5D2400X 54 0x0069 scaler_vstr_offset (default: 0 x 00) r/w 7:6 reserved 5:0 vstr_offset sub-pixel vertical starting point offset for scaling - for scale down : vstr_offset = [ (vias-1) ? (voas ? 1) / vratio ] * 16 - for scale up : vstr_offset = 32 ? [16 * {(2 * 3*voas/vias ? 1 + voas ?1) / vratio ? vias ? 1}] %32
preliminary datasheet S5D2400X 55 6.5 advanced color contrast enhancement (ace) control registers bits register name function 0x0070 bu_h_start_h (default: 0 x 00) r/w 7:3 reserved 2:0 bu_hsp[10:8] boost up area : horizontal start point 0x0071 bu_h_start_l (default: 0 x 00) r/w 7:0 bu_hsp[7:0] boost up area : horizontal start point 0x0072 bu_v_start_h (default: 0 x 00) r/w 7:3 reserved 2:0 bu_vsp [10:8] boost up area : vertical start point 0x0073 bu_v_start_l (default: 0 x 00) r/w 7:0 bu_vsp[7:0] boost up area : vertical start point 0x0074 bu_h_end_h (default: 0 x 00) r/w 7:3 reserved 2:0 bu_hep[10:8] boost up area : horizontal end point 0x0075 bu_h_end_l (default: 0 x 00) r/w 7:0 bu_hep[7:0] boost up area : horizontal end point 0x0076 bu_v_end_h (default: 0 x 00) r/w 7:3 reserved 2:0 bu_vep[10:8] boost up area : vertical end point 0x0077 bu_v_end_l (default: 0 x 00) r/w 7:0 bu_vep[7:0] boost up area : vertical end point - bu_h/ v_start/end point is changed when bu_vep[7:0] is controlled.
preliminary datasheet S5D2400X 56 0x0078 bu_sub_h_start_h (default: 0 x 00) r/w 7 sub_zonesel if (sub_zonesel == 1) then bu_sub_hsp = bu_hsp, bu_sub_vsp = bu_vsp, bu_sub_hep = bu_hep, bu_sub_vep = bu_vep; 6:3 reserved 2:0 bu_sub_hsp[10:8] boost up calculating area : horizontal start point 0x0079 bu_sub_h_start_l (default: 0 x 00) r/w 7:0 bu_sub_hsp [7:0] boost up calculating area : horizontal start point 0x007a bu_sub_v_start_h (default: 0 x 00) r/w 7:3 reserved 2:0 bu_sub_vsp [10:8] boost up calculating area : vertical start point 0x007b bu_sub_v_start_l (default: 0 x 00) r/w 7:0 bu_sub_vsp [7:0] boost up calculating area : vertical start point 0x007c bu_sub_h_end_h (default: 0 x 00) r/w 7:3 reserved 2:0 bu_sub_hep [10:8] boost up calculating area : horizontal end point 0x007d bu_sub_h_end_l (default: 0 x 00) r/w 7:0 bu_sub_hep [7:0] boost up calculating area : horizontal end point 0x007e bu_sub_v_end_h (default: 0 x 00) r/w 7:3 reserved 2:0 bu_sub_vep [10:8] boost up calculating area : vertical end point 0x007f bu_sub_v_end_l (default: 0 x 00) r/w 7:0 bu_sub_vep [7:0] boost up calculating area : vertical end point - bu_sub_h/ v_start/end point is changed when bu_sub_vep[7:0] is controlled
preliminary datasheet S5D2400X 57 0x0080 bu_max_coef (default: 0 x 00) r/w 7:0 max_coeff response time to max 0x0081 bu_min_coef (default: 0 x 00) r/w 7:0 min_coeff response time to min 0x0082 bu_avr_l1_coef (default: 0 x 00) r/w 7:0 avr_l1_coeff avr response time before stretching 0x0083 bu_avr_coef (default: 0 x 00) r/w 7:0 avr_coeff avr response time after stretching 0x0084 bu_max_threshold (default: 0 x 00) r/w 7:4 ymax_high_int upper threshold for max : ymax_high_th >= max >= ymax_low_th 3:0 ymax_low_int lower threshold for max 0x0085 bu_min_threshold (default: 0 x 00) r/w 7:4 ymin_high_int upper threshold for min : ymin_high_th >= min >= ymin_low_th 3:0 ymin_low_int lower threshold for min 0x0086 bu_max_1st (default: 0 x 00) r/w 7:0 ymax_1st_base the number of pixels considered as the biggest value in max 0x0086 bu_max_1st (default: 0 x 00) r/w 7:0 ymax_1st_base the number of pixels considered as the biggest value in max 0x0087 bu_max_2nd (default: 0 x 00) r/w 7:0 ymax_2nd_ base the number of pixels considered as the next biggest value in max when ymax_1st_base condition is not met.
preliminary datasheet S5D2400X 58 0x0088 bu_min_1st (default: 0 x 00) r/w 7:0 ymin_1st_base the number of pixels considered as the smallest value in min 0x0089 bu_min_2 nd (default: 0 x 00) r/w 7:0 ymin_2nd_ base the number of pixels considered as the next smallest value in min when ymin_1 st _base condition is not met. 0x008a bu_avr_l1_h (default: 0 x 00) r/w 7:0 avr_l1_h adjusts the max value. 0x008b bu_avr_l1_l (default: 0 x 00) r/w 7:0 avr_l1_l adjusts the min value. 0x008c bu_level (default: 0 x 00) r/w 7 boost_on on / off (1: on) of stretching and boost 6:1 reserved 0 st_level stretching level (0: low stretch, 1: high stretch) 0x008d bu_minmax_control (default: 0 x 00) r/w 7:5 reserved 4 ymax_ctrl the method of modifying max : (m_max) 0 : not stretching 1 : m_max = 1/8 * max 3:1 reserved 0 ymin_ctrl the method of modifying min : (m_min) 0 : not stretching 1 : m_min = 1/8 * min 0x008e bu_avr_lut_gain (default: 0 x 00) r/w 7:2 reserved 1:0 avr_lut_gain boost gain control by avr and lut
preliminary datasheet S5D2400X 59 0x0090 bu_color_control (default: 0 x 00) r/w 7:6 reserved 5 itu-r.sel itu-r bt.656 offset correction on / off (1: on) 4:2 rgbrate color correction rate (0.5625, 0.625, 0.6875, 0.75, 0.8125, 0.875, 0.9375, 1) 1:0 sel_div selects the color correction method 0 : off 1 : color correction coefficient determining filter 1 2 : color correction coefficient determining filter 2 3 : color correction coefficient determining filter 3 0x0091 bu_aperture_gain (default: 0 x 00) r/w 7:4 reserved 3:0 ap_gain sharpness gain control 0x0094 bu_graph_control (default: 0 x 00) r/w 7:2 reserved 1 gr_mode boost up lut graph on / off (1: on) 0 gr_style boost up lut graph style select (1: bar, 0: line) 0x0095 bu_avr_rate_h (default: 0 x 00) r/w 7:1 reserved 0 avrrate[8] adjusts boost rate (no boost if the bit is 0.) 0x0096 bu_avr_rate_l (default: 0 x 00) r/w 7:0 avrrate[7:0] adjusts boost rate (no boost if the bit is 0.) avrrate[8:0] binary number. only the first 1 bit is constant. for example, 9bits is expressed as x.xxxxxxxx. the minimum must be 0.5. 0x0097 bu_filter_control (default: 0 x 00) r/w 7:6 reserved 5 area_on boost border line including screen outer line (1: on, 0: off) 4:0 reserved
preliminary datasheet S5D2400X 60 6.6 global image gain & offset control register bits register name function 0x00d0 contrast_control_type (default: 0 x 01f) r/w 7:6 reserved 5:4 cont_type determines magnification of the contrast control area 00: 0 ~ 0.99609375, 01: 0.5 ~ 1.49609375 (default) 10: 0 ~ 1.9921875, 11: 0 ~ 3.984375 3 zone_ct zone area control type 1: adjusts global/zone together based on global (default) 0: adjusts global/zone separately 2 black_ct black level control type 1: adjusts r/g/b together based on r (default) 0: adjusts r/g/b separately 1 cont_ct contrast control type 1: adjusts r/g/b together based on r (default) 0: adjusts r/g/b separately 0 bright_ct brightness control type 1: adjusts r/g/b together based on r (default) 0: adjusts r/g/b separately 0x00d1 contrast_r_black_global (default: 0 x 00) r/w 7:6 reserved 5:0 r_black_global adjusts r channel black level. r/g/b are adjusted separately if black_ct (addr 0x00d0[2]) is 0, and are adjusted together based on r if it is 1. 0x00d2 contrast_g_black_global (default: 0 x 00) r/w 7:6 reserved 5:0 g_black_global adjusts g channel black level. r/g/b are adjusted separately if black_ct (addr 0x00d0[2]) is 0, and are adjusted together based on r if it is 1. 0x00d3 contrast_b_black_global (default: 0 x 00) r/w 7:6 reserved 5:0 b_black_global adjusts b channel black level. r/g/b are adjusted separately if black_ct(addr 0x00d0[2]) is 0, and are adjusted together based on r if it is 1.
preliminary datasheet S5D2400X 61 0x00d4 contrast_r_cont_global (default: 0 x 80) r/w 7:0 r_cont_global adjusts r channel contrast. r/g/b are adjusted separately if cont_ct(addr 0x00d0[1]) is 0, and are adjusted together based on r if it is 1. 0x00d5 contrast_g_cont_global (default: 0 x 80) r/w 7:0 g_cont_global adjusts g channel contrast. r/g/b are adjusted separately if cont_ct(addr 0x00d0[1]) is 0, and are adjusted together based on r if it is 1. 0x00d6 contrast_b_cont_global (default: 0 x 80) r/w 7:0 b_cont_global adjusts b channel contrast. r/g/b are adjusted separately if cont_ct(addr 0x00d0[1]) is 0, and are adjusted together based on r if it is 1. 0x00d7 contrast_r_bright_global (default: 0 x 00) r/w 7:0 r_bright_global adjusts r channel brightness. r/g/b are adjusted separately if bright_ct(addr 0x00d0[0]) is 0, and are adjusted together based on r if it is 1. 0x00d8 contrast_g_bright_global (default: 0 x 00) r/w 7:0 g_bright_global adjusts g channel brightness. r/g/b are adjusted separately if bright_ct (addr 0x00d0[0]) is 0, and are adjusted together based on r if it is 1. 0x00d9 contrast_b_bright_global (default: 0 x 00) r/w 7:0 b_bright_global adjusts b channel brightness. r/g/b are adjusted separately if bright_ct (addr 0x00d0[0]) is 0, and are adjusted together based on r if it is 1. 0x00da contrast_b_black_zone (default: 0 x 00) r/w 7:6 reserved 5:0 r_black_zone adjusts r channel black level in the boot area
preliminary datasheet S5D2400X 62 0x00db contrast_b_black_zone (default: 0 x 00) r/w 7:6 reserved 5:0 g_black_zone adjusts g channel black level in the boot area 0x00dc contrast_b_black_zone (default: 0 x 00) r/w 7:6 reserved 5:0 b_black_zone adjusts b channel black level in the boot area 0x00dd contrast_r_cont_zone (default: 0 x 80) r/w 7:0 r_cont_zone adjusts r channel contrast in the boot area 0x00de contrast_g_cont_zone (default: 0 x 80) r/w 7:0 g_cont_zone adjusts g channel contrast in the boot area 0x00df contrast_b_cont_zone (default: 0 x 80) r/w 7:0 b_cont_zone adjusts b channel contrast in the boot area 0x00e0 contrast_r_bright_zone (default: 0 x 00) r/w 7:0 r_bright_zone adjusts r channel brightness in the boot area 0x00e1 contrast_g_bright_zone (default: 0 x 00) r/w 7:0 g_bright_zone adjusts g channel brightness in the boot area 0x00e2 contrast_b_bright_zone (default: 0 x 00) r/w 7:0 b_bright_zone adjusts b channel brightness in the boot area 0x00e3 contrast_bg_color_r (default: 0 x 00) r/w 7:6 reserved 5 bg_color enable background color (1: on, 0: off) - background color correspond to bg_color_r,g,b color pallet - highest priority in color control. 4:0 bg_color_r r channel background color
preliminary datasheet S5D2400X 63 0x00e4 contrast_bg_color_g (default: 0 x 00) r/w 7:5 reserved 4:0 bg_color_g g channel background color 0x00e5 contrast_bg_color_b (default: 0 x 10) r/w 7:5 reserved 4:0 bg_color_b b channel background color
preliminary datasheet S5D2400X 64 6.7 osd control registers bits register name function 0x0100 osd_char_tone (default: 0 x 60) r/w 7 osd_en osd output enable (1: enable, 0: disable) 6 dsram_clrn dsram clear (1: no operation, 0: active) 5 ftram_clrn font ram clear (1: no operation, 0: active) 4 itensity intensity select 3 ch_tone character half toning : if (osd_tone[2] == 0 && osd_tone[1:0] != 0 && ch_tone == 1) then if half tone (transparency) is enabled, it is applied to the font area. 2:0 osd_tone osd half toning : 0: osd bypass and input image are expressed. (default) 1: input image and osd are mixed at the rate of 0.25. 2: input image and osd are mixed at the rate of 0.5. 3: input image and osd are mixed at the rate of 0.75. 4 or higher : only osd is expressed without mixing with the input image. 0x0101 osd_font_size (default: 0 x 00) r/w 7:6 ch_hsz determines, based on the font size (12 18), the magnifying rate of the character horizontal size. - for example, if ch_hsz is set to 1, the horizontal size of the character becomes 12 2 pixel. (00: 12 1, 01: 12 2, 10: 12 3, 11: 12 4) 5:4 ch_vsz determines, based on the font size (12 18), the magnifying rate of the character vertical size. - for example, if ch_vsz is set to 3, the vertical size of the character becomes 18 4 pixel. (00: 18 1, 01: 18 2, 10: 18 3, 11: 18 4) 3:0 row_sp controls the number of row spaces between the upper and lower fonts. the row space is expressed in interworking with vertical pixels in accordance with the character vertical size. - for example, if row_sp is 2 and ch_vsz is 2, the row space is 6 lines.
preliminary datasheet S5D2400X 65 0x0102 osd_hfont (default: 0 x 00) r/w 7:6 reserved 5:0 osd_hfont the number of horizontal fonts of osd - if osd_hfont is 30, the number of horizontal fonts of osd is 30. 0x0103 osd_vfont (default: 0 x 00) r/w 7:6 reserved 5:0 osd_vfont the number of vertical fonts of osd. - if osd_vfont is 15, the number of vertical fonts of osd is 15. 0x0104 osd_hsp_h (default: 0 x 00) r/w 7:3 reserved 2:0 osd_hsp[10:8] sets the horizontal start point of osd. - if w_bdsh_en is 1, and if osd_hsp is lower than 6 as w_bdsh is 1, osd_hsp is 6. 0x0105 osd_hsp_l (default: 0 x 00) r/w 7:0 osd_hsp[7:0] sets the horizontal start point of osd. 0x0106 osd_vsp_h (default: 0 x 00) r/w 7:3 reserved 2:0 osd_vsp[10:8] sets vertical start point of osd. - if w_bdsh_en is 1, and osd_vsp is lower than 6 as w_bdsh is 1, osd_vsp is 6. 0x0107 osd_vsp_l (default: 0 x 00) r/w 7:0 osd_vsp[7:0] sets the vertical start point of osd.
preliminary datasheet S5D2400X 66 0x0108 osd_border_shadow (default: 0 x 00) r/w 7:5 reserved 4 w_bdsh_en controls osd main window border / shadow enable 1: enables osd main window border / shadow 0: osd main window border / shadow is disappeared regardless of w_bdsh 3 w_bdsh border and shadow of osd window is determined by setting w_bdsh to o or 1 as w_bdsh_en(addr 0x0108[4]) is 1. (1: osd main window bordering, 0: osd main window shadow) 2 mw_bdsh_en controls border / shadow enable of multiple windows. 1: enables osd multiple windows border / shadow 0: multiple window border / shadow is disappeared regardless of mw_bdsh 1 mw_bdsh border and shadow of osd window is determined by setting mw_bdsh to 0 or 1 as mw_bdsh_en(addr 0x0108[2]) is 1. (1: osd multiple window bordering, 0: osd multiple window shadow) 0 ch_bdsh_en controls character border/shadow enable 1: character border if dsram[15] is 1, and character shadow if 0 0: border / shadow are disabled regardless of dsram[15]. 0x0109 osd_mw_enable (default: 0 x 00) r/w 7:4 reserved 3 w1_en multiple windows 1 enable control 1: lut color of w1c is expressed in multiple windows 1 0: multiple windows 1 is disabled. 2 w2_en multiple windows 2 enable control. 1: lut color of w2c is expressed in multiple windows 2 0: multiple windows 2 is disabled. 1 w3_en multiple windows 3 enable control. 1: lut color of w3c is expressed in multiple windows 3 0: multiple windows 3 is disabled. 0 w4_en multiple windows 4 enable control. 1: lut color of w4c is expressed in multiple windows 4 0: multiple windows 4 is disabled.
preliminary datasheet S5D2400X 67 0x010a osd_mw_priority (default: 0 x 00) r/w 7:6 w1_prt sets priority of w1 in 4 multiple windows - the priority order is w1, w2, w3 and w4 if the same priority is given. (0: highest priority, 1: 2nd priority, 2: 3rd priority, 2: 4th priority) 5:4 w2_prt sets priority of w2 in 4 multiple windows - the priority order is w1, w2, w3 and w4 if the same priority is given. (0: highest priority, 1: 2nd priority, 2: 3rd priority, 2: 4th priority) 3:2 w3_prt sets priority of w3 in 4 multiple windows - the priority order is w1, w2, w3 and w4 if the same priority is given. (0: highest priority, 1: 2nd priority, 2: 3rd priority, 2: 4th priority) 1:0 w4_prt sets priority of w4 in 4 multiple windows - the priority order is w1, w2, w3 and w4 if the same priority is given. (0: highest priority, 1: 2nd priority, 2: 3rd priority, 2: 4th priority) 0x010b osd_bdsh_color (default: 0 x 00) r/w 7:6 reserved 5:4 wsh_c selects shadow color of osd main/ multiple windows 0: lut12[3:0] is applied to windows shadow color 1: lut13[3:0] is applied to windows shadow color 2: lut14[3:0] is applied to windows shadow color 3: lut15[3:0] is applied to windows shadow color 3:0 ch_bsc selects character border / shadow color as ch_bdsh_en (addr 0x0108[0] is 1. you can select from lut0 to lut15 in this way. 0: lut0[7:4] is used as the border / shadow color of the character 1: lut1[7:4] is used as border / shadow color of the character 2: lut2[7:4] is used as border / shadow color of the character 3: lut3[7:4] is used as border / shadow color of the character
preliminary datasheet S5D2400X 68 0x010c osd_shadow_size_mcf (default: 0 x 00) r/w 7:6 reserved 5:4 wsh_sz controls the window shadow size as w_bdsh_en (addr 0x0108[4]) is 1 and w_bdsh(addr 0x0108[3]) is 0. 0. horizontal/vertical shadow size of the osd main window is 1 pixel in both horizontal and vertical. 1. horizontal/vertical shadow size of the osd main window is 2 pixel in both horizontal and vertical. 2. horizontal/vertical shadow size of the osd main window is 3 pixel in both horizontal and vertical. 3. horizontal/vertical shadow size of the osd main window is 4 pixel in both horizontal and vertical. controls the window shadow size as mw_bdsh_en (addr 0x0108[2]) is 1 and mw_bdsh(addr 0x0108[1]) is 0. horizontal/vertical shadow size of the multiple windows are the same as osd main window. 3:0 n_mcf number of multi-colored ram font - up to 9 multi color fonts are available out of 28 ram fonts. when considering r/g/b, up to 27 fonts (9x3) are available, and single color font is used for the remaining 1 font. if 4 mcfs are used, 4*3 = 12 fonts out of 28 ram fonts are used for mcf, and remaining 16 fonts can be used for sf. 0x010d osd_blink_control (default: 0 x 00) r/w 7:5 reserved 4:2 blnk_sel blink duty select: 0: off 32 frame (about 0.5sec) / on 32 frame (about 0.5sec) 1: off 64 frame (about 1sec) / on 32 frame (about 0.5sec) 2: off 32 frame (about 0.5sec) / on 64 frame (about 1sec) 3: off 64frame (about 1sec) / on 64 frame (about 1sec) 4: off 96 frame (about 1.5sec) / on 96frame (about 1.5sec) 5: off 128 frame (about 2sec) / on 64 frame (about 1sec) 6: off 64 frame (about 1sec) / on 128 frame (about 2sec) 7: off 128 frame (about 2sec) / on 128 frame (about 2sec) 1 bl_ntra blink or no_tone_raster: 1: if display ram[14] is 1, blink according to blnk_sel 0: if display ram[14] is 0, half tone is not applied to the raster part. in this case, border/shadow of character is disabled. 0 blnk_c blink color inversion: 1: if blink is off, the complementary color of raster is displayed in the character part. 0: if blink is off, the raster color is displayed in the character part.
preliminary datasheet S5D2400X 69 0x010e osd_w1_w2_color (default: 0 x 00) r/w 7:4 w1c multiple windows 1 color. - if w1_en (addr 0x0109[3]) is 1 and n(0~15) is selected for w1c, lutn[3:0] is assigned for multiple windows 1. for example, if w1c is 7 then lut7[3:0] is assigned for the color of windows multiple windows 1. 3:0 w2c multiple windows 2 color. - if w2_en (addr 0x0109[2]) is 1 and n(0~15) is selected for w2c, lutn[3:0] is assigned for multiple windows 2. 0x010f osd_w3_w4_color (default: 0 x 00) r/w 7:4 w3c multiple windows 3 color. - if w3_en (addr 0x0109[1]) is 1 and n(0~15) is selected for w3c, lutn[3:0] is assigned for multiple windows 3. 3:0 w4c multiple windows 4 color. - if w4_en (addr 0x0109[0]) is 1 and n(0~15) is selected for w4c, lutn[3:0] is assigned for multiple windows 4. 0x0110 osd_w1_row_str (default: 0 x 00) r/w 7:5 reserved 4:0 w1r_str row start position (1(not 0) ~ 31) of multiple windows 1 - if the bit is 1, y of the start (x, y) of multiple windows 1 is 1 0x0111 osd_w1_row_end (default: 0 x 00) r/w 7:5 reserved 4:0 w1r_end row end position (1(not 0) ~ 31) of multiple windows 1 - if the bit is 2, y of the end (x, y) of multiple windows 1 is 2 0x0112 osd_w1_column_str (default: 0 x 00) r/w 7:6 reserved 5:0 w1c_str column start position (1(not 0) ~ 63) of multiple windows 1 - if the bit is 1, x of the start (x, y) of multiple windows 1 is 1 0x0113 osd_w1_column_end (default: 0 x 00) r/w 7:6 reserved 5:0 w1c_end column end position (1(not 0) ~ 63) of multiple windows 1 - if the bit is 2, x of the end (x, y) of multiple windows 1 is 2
preliminary datasheet S5D2400X 70 0x0114 osd_w2_row_str (default: 0 x 00) r/w 7:5 reserved 4:0 w2r_str row start position (1(not 0) ~ 31) of multiple windows 2 - if the bit is 1, y of the start (x, y) of multiple windows 2 is 1 0x0115 osd_w2_row_end (default: 0 x 00) r/w 7:5 reserved 4:0 w2r_end row end position (1(not 0) ~ 31) of multiple windows 2 - if the bit is 2, y of the end (x, y) of multiple windows 2 is 2 0x0116 osd_w2_column_str (default: 0 x 00) r/w 7:6 reserved 5:0 w2c_str column start position (1(not 0) ~ 63) of multiple windows 2 - if the bit is 1, x of the start (x, y) of multiple windows 2 is 1 0x0117 osd_w2_column_end (default: 0 x 00) r/w 7:6 reserved 5:0 w2c_end column end position (1(not 0) ~ 63) of multiple windows 2 - if the bit is 2, x of the end (x, y) of multiple windows 2 is 2 0x0118 osd_w3_row_str (default: 0 x 00) r/w 7:5 reserved 4:0 w3r_str row start position (1(not 0) ~ 31) of multiple windows 3 - if the bit is 1, y of the start (x, y) of multiple windows 3 is 1 0x0119 osd_w3_row_end (default: 0 x 00) r/w 7:5 reserved 4:0 w3r_end row end position (1(not 0) ~ 31) of multiple windows 3 - if the bit is 2, y of the end (x, y) of multiple windows 3 is 2 0x011a osd_w3_column_str (default: 0 x 00) r/w 7:6 reserved 5:0 w3c_str column start position (1(not 0) ~ 63) of multiple windows 3 - if the bit is 1, x of the start (x, y) of multiple windows 3 is 1
preliminary datasheet S5D2400X 71 0x011b osd_w3_column_end (default: 0 x 00) r/w 7:6 reserved 5:0 w3c_end column end position (1(not 0) ~ 63) of multiple windows 3 - if the bit is 2, x of the start (x, y) of multiple windows 3 is 2 0x011c osd_w4_row_str (default: 0 x 00) r/w 7:5 reserved 4:0 w4r_str row start position (1(not 0) ~ 31) of multiple windows 4 - if the bit is 1, y of the start (x, y) of multiple windows 4 is 1 0x011d osd_w4_row_end (default: 0 x 00) r/w 7:5 reserved 4:0 w4r_end row end position (1(not 0) ~ 31) of multiple windows 4 - if the bit is 2, y of the end (x, y) of multiple windows 4 is 2 0x011e osd_w4_column_str (default: 0 x 00) r/w 7:6 reserved 5:0 w4c_str column start position (1(not 0) ~ 63) of multiple windows 4 - if the bit is 1, x of the start (x, y) of multiple windows 4 is 1 0x011f osd_w4_column_end (default: 0 x 00) r/w 7:6 reserved 5:0 w4c_end column end position (1(not 0) ~ 63) of multiple windows 4 - if the bit is 2, x of the end (x, y) of multiple windows 4 is 2 0x0120 osd_lut0 (default: 0 x 00) r/w 7:0 lut0 look up table 0 (lut0[7:4]: font character color (7: r, 6: g, 5: g, 4: b) lut0[3:0]: raster font color (3: r, 2: g, 1: g, 0: b)) 0x0121 osd_lut1 (default: 0 x 00) r/w 7:0 lut1 look up table 1 (lut1[7:4]: font character color, lut1[3:0]: font raster color)
preliminary datasheet S5D2400X 72 0x0122 osd_lut2 (default: 0 x 00) r/w 7:0 lut2 look up table 2 (lut2[7:4]: font character color, lut2[3:0]: font raster color) 0x0123 osd_lut3 (default: 0 x 00) r/w 7:0 lut3 look up table 3 (lut3[7:4]: font character color, lut3[3:0]: font raster color) 0x0124 osd_lut4 (default: 0 x 00) r/w 7:0 lut4 look up table 4 (lut4[7:4]: font character color, lut4[3:0]: font raster color) 0x0125 osd_lut5 (default: 0 x 00) r/w 7:0 lut5 look up table 5 (lut5[7:4]: font character color, lut5[3:0]: font raster color) 0x0126 osd_lut6 (default: 0 x 00) r/w 7:0 lut6 look up table 6 (lut6[7:4]: font character color, lut6[3:0]: font raster color) 0x0127 osd_lut7 (default: 0 x 00) r/w 7:0 lut7 look up table 7 (lut7[7:4]: font character color, lut7[3:0]: font raster color) 0x0128 osd_lut8 (default: 0 x 00) r/w 7:0 lut8 look up table 8 (lut8[7:4]: font character color, lut8[3:0]: font raster color) 0x0129 osd_lut9 (default: 0 x 00) r/w 7:0 lut9 look up table 9 (lut9[7:4]: font character color, lut9[3:0]: font raster color)
preliminary datasheet S5D2400X 73 0x012a osd_lut10 (default: 0 x 00) r/w 7:0 lut10 look up table 10 (lut10[7:4]: font character color, lut10[3:0]: font raster color) 0x012b osd_lut11 (default: 0 x 00) r/w 7:0 lut11 look up table 11 (lut11[7:4]: font character color, lut11[3:0]: font raster color) 0x012c osd_lut12 (default: 0 x 00) r/w 7:0 lut12 look up table 12 (lut12[7:4]: font character color, lut12[3:0]: font raster color) 0x012d osd_lut13 (default: 0 x 00) r/w 7:0 lut13 look up table 13 (lut13[7:4]: font character color, lut13[3:0]: font raster color) 0x012e osd_lut14 (default: 0 x 00) r/w 7:0 lut14 look up table 14 (lut14[7:4]: font character color, lut14[3:0]: font raster color) 0x012f osd_lut15 (default: 0 x 00) r/w 7:0 lut15 look up table 15 (lut15[7:4]: font character color, lut15[3:0]: font raster color) 0x43ef font_ram_en r/w 7:6 reserved 0 ftram_en font ram enable (1: enable, 0: disable) writes data on the font ram, and enables it.
preliminary datasheet S5D2400X 74 6.8 gamma correction control register bits register name function default 0x0150 gam_r_lut_1_2 r/w : : : 0x016f gam_r_lut_31_32 r/w 7:0 ryav1 red output (y) axis value for input (x) axis 8'h08 7:0 ryav2 value 8, 16, 24, 32, . . . , 240, 248, 255 8'h10 7:0 ryav3 8'h18 7:0 ryav4 8'h20 7:0 ryav5 8'h28 7:0 ryav6 8'h30 7:0 ryav7 8'h38 7:0 ryav8 8'h40 7:0 ryav9 8'h48 7:0 ryav10 8'h50 7:0 ryav11 8'h58 7:0 ryav12 8'h60 7:0 ryav13 8'h68 7:0 ryav14 8'h70 7:0 ryav15 8'h78 7:0 ryav16 8'h80 7:0 ryav17 8'h88 7:0 ryav18 8'h90 7:0 ryav19 8'h98 7:0 ryav20 8'ha0 7:0 ryav21 8'ha8 7:0 ryav22 8'hb0 7:0 ryav23 8'hb8 7:0 ryav24 8'hc0 7:0 ryav25 8'hc8 7:0 ryav26 8'hd0 7:0 ryav27 8'hd8 7:0 ryav28 8'he0 7:0 ryav29 8'he8 7:0 ryav30 8'hf0 7:0 ryav31 8'hf8 7:0 ryav32 8'hff 0 ryav1 ryav2 ryav3 ryav4 ryav30 ryav31 ryav32 x y 8 16 24 32 . . . . . . . . . . 240, 248, 255
preliminary datasheet S5D2400X 75 bits register name function default 0x0170 gam_g_lut_1_2 r/w : : : 0x018f gam_g_lut_31_32 r/w 7:0 gyav1 green output (y) axis value for input (x) axis 8'h08 7:0 gyav2 value 8, 16, 24, 32, . . . , 240, 248, 255 8'h10 7:0 gyav3 8'h18 7:0 gyav4 8'h20 7:0 gyav5 8'h28 7:0 gyav6 8'h30 7:0 gyav7 8'h38 7:0 gyav8 8'h40 7:0 gyav9 8'h48 7:0 gyav10 8'h50 7:0 gyav11 8'h58 7:0 gyav12 8'h60 7:0 gyav13 8'h68 7:0 gyav14 8'h70 7:0 gyav15 8'h78 7:0 gyav16 8'h80 7:0 gyav17 8'h88 7:0 gyav18 8'h90 7:0 gyav19 8'h98 7:0 gyav20 8'ha0 7:0 gyav21 8'ha8 7:0 gyav22 8'hb0 7:0 gyav23 8'hb8 7:0 gyav24 8'hc0 7:0 gyav25 8'hc8 7:0 gyav26 8'hd0 7:0 gyav27 8'hd8 7:0 gyav28 8'he0 7:0 gyav29 8'he8 7:0 gyav300 8'hf0 7:0 gyav31 8'hf8 7:0 gyav32 8'hff 0 gyav1 gyav2 gyav3 gyav4 gyav30 gyav31 gyav32 x y 8 16 24 32 . . . . . . . . . . 240, 248, 255
preliminary datasheet S5D2400X 76 bits register name function default 0x0190 gam_b_lut_1_2 r/w : : : 0x01af gam_b_lut_31_32 r/w 7:0 byav1 blue output (y) axis value for input (x) axis 8'h08 7:0 byav2 value 8, 16, 24, 32, . . . , 240, 248, 255 8'h10 7:0 byav3 8'h18 7:0 byav4 8'h20 7:0 byav5 8'h28 7:0 byav6 8'h30 7:0 byav7 8'h38 7:0 byav8 8'h40 7:0 byav9 8'h48 7:0 byav10 8'h50 7:0 byav11 8'h58 7:0 byav12 8'h60 7:0 byav13 8'h68 7:0 byav14 8'h70 7:0 byav15 8'h78 7:0 byav16 8'h80 7:0 byav17 8'h88 7:0 byav18 8'h90 7:0 byav19 8'h98 7:0 byav20 8'ha0 7:0 byav21 8'ha8 7:0 byav22 8'hb0 7:0 byav23 8'hb8 7:0 byav24 8'hc0 7:0 byav25 8'hc8 7:0 byav26 8'hd0 7:0 byav27 8'hd8 7:0 byav28 8'he0 7:0 byav29 8'he8 7:0 byav30 8'hf0 7:0 byav31 8'hf8 7:0 byav32 8'hff 0 byav1 byav2 byav3 byav4 byav30 byav31 byav32 x y 8 16 24 32 . . . . . . . . . . 240, 248, 255
preliminary datasheet S5D2400X 77 6.9 osd ram control registers address bits register name function 0x1000 ~ 0x10ff 7:0 bu_lut acce look up table 0x2000 ~ 0x2383 15:0 osd_dspram display ram ( 450 16 bits ) for osd 0x3fff ~ 0x43ee 11:0 osd_fontram font ram for osd, 28 fonts ( 1fonts = 18 12 bits ) 0x43ef 0 ftram_en font ram enable (1: enable, 0: disable) writes data on the font ram, and enables it.
preliminary datasheet S5D2400X 78 7 electrical specification 7.1 absolute maximum ratings table 8. absolute maximum ratings characteristics symbol rating unit dc supply voltage v dd 1.8v v dd 2.7 v 3.3v v dd 3.8 dc input voltage v in 3.3v input buffer 3.8 3.3v interface / 5v tolerant input buffer 6.5 dc output voltage v out 3.3v output buffer 2.7 1.8v interface / 3.3v tolerant output buffer 3.8 latch up current i latch 100 ma storage temperature t stg plastic - 65 to 150 c 7.2 recommended operation conditions table 9. recommended operating conditions characteristics symbol rating unit dc supply voltage v dd 1.8v v dd 1.8 0.15 v 3.3v v dd 3.3 0.3 dc input voltage v in 3.3v input buffer 3.3 0.3 3.3v interface / 5v tolerant input buffer 3.0 ~ 5.25 dc output voltage v out 3.3v output buffer 3.3 0.3 1.8v interface / 3.3v tolerant output buffer 1.8 0.15 operating temperature t a commercial 0 to 70 c
preliminary datasheet S5D2400X 79 7.3 dc electrical characteristics vdd1 = 3.3v 0.3v, vdd2 = vdda = 1.8v 0.15v, ta = 25 c table 10. dc electrical characteristics at 3.3v item symbol condition min typ max unit remark supply digital power 1 v dd v dd1 3.0 3.3 3.6 v *1 voltage digital power 2 v dd2 1.65 1.8 1.95 v *2 analog power v dda 1.65 1.8 1.95 v *3 input high level v ih 2.0 v *4 voltage low level v il 0.8 v output high level v oh i oh = -2ma 2.4 v *5 voltage i oh = -4ma 2.4 v *6 i oh = -20ma 2.4 v *7 low level v ol i ol = 2ma 0.4 v *5 i ol = 4ma 0.4 v *6 i ol = 20ma 0.4 v *7 schmitt positive-going threshold vt+ cmos 2.0 v *8 trigger negative-going threshold vt - cmos 0.8 v input high input buffer i ih v in = v dd -10 10 m a *9 current level input buffer with pull-down 10 33 60 m a *10 low level input buffer i il vin = vss -10 10 m a *9 tri-state output leakage current i oz v out = v ss or v dd -10 10 m a *11 power consumption pd 900 mw [remark] *1 : pin 10, 39, 76 *2 : pin 21, 57, 94 *3 : pin 15, 19 *4 : all input pins *5 : pin 58, 59, 60 *6 : pin 1~2, 8, 31~38, 40~47, 49~56, 73~75, 77~84, 86~93, 95~100 *7 : pin 72 *8 : pin 6~9, 61~65 * 9 : pin 6~9, 11, 20, 22~29, 61~65, 67~68 * 10 : pin 4~5, 31~38, 40~47, 49~56, 69~71 * 11 : pin 1~2, 31~38, 40~47, 49~56, 77~84, 86~93, 95~100
preliminary datasheet S5D2400X 80 7.4 ac electrical characteristics 7.4.1 video input timing characteristics valid data valid data valid data t su t vh t vl t v (= 1 / f v ) vi0 - 7, ri0 - 7, gi0 - 7, bi0 - 7, ghs, gvs, fld vck t hd item symbol min typ max units setup time to vck, input vi0~7, rio0~7, gio0~7, bio0~7, ghs, gvs, fld t su 2.0 ns hold time to vck, input vi0~7, rio0~7, gio0~7, bio0~7, ghs, gvs, fld t hd 2.0 ns input frequency f v 90 mhz input high duration time t vh 3.0 ns input low duration time t vl 3.0 ns
preliminary datasheet S5D2400X 81 7.4.2 display output timing characteristics pcko (pcko_phase[2] = 0) pcko (pcko_phase[2] = 1) t d (= 1 / f d ) 90% 10% tr tf t pd ro0~7, go0~7, bo0~7, phso, pvso, pden t pd valid data valid data item symbol min typ max units propagation delay time from pcko, output ro0~7, go0~7, bo0~7, phso, pvso, pden t pd - 3 0 3 ns frequency, output display clock pcko f d 100 mhz duty cycle, output display clock pcko c duty 45 50 55 % rise time, output display clock pcko t r 3 ns fall time, output display clock pcko t f 3 ns
preliminary datasheet S5D2400X 82 8 package dimension 8.1 100-tqfp-1414 #100 14.00 16.00 bsc 14.00 16.00 bsc 0.08 max 0.09 - 0.20 0-7 note : dimensions are in millimeters. #1 0.50 (1.00) 0.60 + 0.15 0.05 - 0.15 1.00 + 0.05 1.20 max 0.17 - 0.27 0.08 max
preliminary datasheet S5D2400X 83 9 fonts
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